This invention relates generally to a system and method for routing data packets in a data communications network, and in particular to a system and method for processing header portions of data packets in order to route the data packets through the data communications network.
The amount of Internet Protocol (IP) data packet traffic being communicated over the Internet, as well as Intranets, has grown exponentially over the past decade. Communications networks are constantly being expanded to handle this growth. The expansion of the communications networks is typically accomplished by partitioning a network that is too large into a number of smaller communication networks in which each smaller network is serviced by a separate router, and then relinking the smaller partitioned networks back together with inter-networking equipment. However, even with this cycle of partitioning and relinking of communication networks, in some environments, such as large-scale public and private data backbones, the data packet traffic has reached such tremendous amounts that these conventional routers cannot handle the data packet traffic and proposed enhancements to these conventional routers cannot keep pace with the ever increasing amount of data packet traffic.
Normally, a conventional router is used in a communications network to route data packets through the network from a first location, known as a source, to a second location, known as a destination. These conventional routers typically have a single shared data bus so that each data packet received by the router must wait for access to the shared bus before being forwarded to the next network "hop" along the data path to the destination address of the data packet. A portion of a route table for a router, which is used to determine the next network hop for a data packet, is typically stored in a cache memory. The portion of the route table stored in the cache memory is typically the most frequently used next network addresses. Using the route table data stored in the cache, the router attempts to determine the next network address for a particular data packet. If the next network address of the data packets is not contained in the portion of the route table in the cache, the data packet is further delayed while a complete software-based route table look-up is performed. If the route table is large, the delay caused by the full software route table look-up may be substantial. Thus, the delay associated with contention for the shared bus and the route table caching and look-up problems of conventional routers lead to poor data packet transfer performance or lost data packets when a conventional router is placed in a large, dynamic network, such as the Internet. Thus, these conventional routers cannot achieve the data packet processing rates necessary for the future needs of the Internet and other high speed computer networks.
Instead of a conventional router with a shared bus architecture, a new class of the network switches and packet processing systems have been developed that attempt to efficiently process and transfer data packets through a switch to the next hop network. These packet processing systems attempt to overcome the problems with a conventional router by processing data packets more rapidly than conventional routers. The speed of the processing of the data packets may be increased in a number of different ways. For example, one conventional packet processing system and method receives an incoming data packet and splits the incoming data packet into a header portion and a data portion. The data portion is stored in a conventional buffer memory while the header portion is stored in a cache memory which has a faster access time than the buffer memory. The cache memory permits the processor to rapidly access the header portions of data packets. The quicker access to the header portions of the data packets, since the processor needs to process the header portion to determine the next hop network address for a data packet, increases the data packet processing speed. Since the processor does not need quick access to the data portion to process a data packet, the storage of the data portions in a slower access buffer memory is acceptable. Once the next hop network address has been determined, the header portion and the corresponding data portion are combined back together and the data packet is sent on to its next hop network. Although the header portion is stored in a fast access time cache memory, the time it takes for the processor to access the cache memory is still slow and ultimately limits the overall processing speed of the packet processing system. In addition, the time required to access a route table in these systems is slow.
Thus, there is a need for a system and method for processing data packets which avoid these and other problems of known systems and methods, and it is to this end that the present invention is directed.